Jespers P. The gmID Methodology.A Sizing Tool.CMOS Circuits 2010 torrent

Textbook in PDF format

IC designers appraise currently transistors sizes while having to fulfill simultaneously a large number of objectives like a prescribed gain-bandwidth product, minimal power consumption, minimal area, low-voltage design, dynamic range, non-linear distortion, etc. Making appropriate decisions is not always obvious. How to meet gain-bandwidth specifications while minimizing power consumption of an Op. Amp without area penalty? Should moderate inversion be preferred to strong inversion? Is sizing an art or a mixture of design experience and repeated simulations? Or is it a constrained multivariate optimization problem? Optimization algorithms are attractive without doubt but they require translating not always well-defined concepts into mathematical expressions. The interactions amid semiconductor physics and systems are not always easy to implement. The objective of the book is to devise a methodology enabling to fix currents and transistors widths of CMOS analog circuits so as to meet specifications such as gain-bandwidth while optimizing attributes like low power and small area. A special attention is given to low-voltage circuits. The sizing method takes advantage of the gm=ID ratio and makes use of either ‘semi-empirical’ data or compact models. The ‘semi-empirical’ approach utilizes large look-up tables derived from physical measurements carried out on real transistors or advanced models. The compact model approach offers the possibility to make use of analytic expressions. Unfortunately when it comes to real transistors, especially sub-micron devices, this isn’t true anymore. Other means are necessary to keep track of high order effects without the risk to loose the inherent simplicity of compact models. Bias dependent instead of constant parameters offer the possibility to extend the validity of a model like the E.K.V. model