Advanced Silicon Test & DFT Methodologies https://WebToolTip.com Published 3/2026
Created by Davide Negri
MP4 | Video: h264, 1920x1080 | Audio: AAC, 44.1 KHz, 2 Ch
Level: Expert | Genre: eLearning | Language: English | Duration: 35 Lectures ( 4h 38m ) | Size: 4.1 GB
Master scan architectures, JTAG, fault models, compression, OCC, MBIST and full tapeout DFT sign-off with Tessent & tmax
What you'll learn
✓ Master fault models, scan architectures, JTAG, test compression, at-speed testing, MBIST, and STIL protocol files.
✓ Implement scan chains, lock-up latches, OCC, and DRC rules using Siemens Tessent and Synopsys TetraMAX.
✓ Analyze ATPG reports: Fault Coverage, Test Coverage, ATPG Effectiveness, and fault classification for tapeout sign-off.
✓ Architect a complete DFT solution from RTL to ATE, including low-power DFT, ISO 26262, and fault diagnosis flows.
Requirements
● Solid RTL design knowledge and digital logic fundamentals. Basic familiarity with synthesis flow and setup/hold timing.